(1) Field of the Invention
The invention relates to a method of reducing thermal stress after metallization in an integrated circuit device, and more particularly, to a method of reducing thermal stress after metallization by formation of a porous intermetal dielectric layer of an integrated circuit device.
(2) Description of the Prior Art
Conventional integrated circuit processes are designed to be void free in the layered structure before and after metal deposition to avoid the electro/stress migration of metal. For example, U.S. Pat. No. 5,099,304 to Takemura et al discloses the formation of voids in his Prior Art as being undesirable.
However, the stress inherently comes from the thermal coefficient difference of expansion between the layers. The stress in a layer can be represented by the following: EQU S.sub.t =(a.sub.f -a.sub.m) (T.sub.r -T.sub.o) E
where S.sub.t is the stress of the current layer measured at room temperature,
a.sub.f and a.sub.m are thermal coefficients of expansion for this layer and the substrate, respectively (substrate here is defined to be the combination of all layers, including the silicon wafer, under this layer) PA1 T.sub.r is the temperature of the layer to be thermally treated, or the formation temperature, PA1 T.sub.o is room temperature, i.e. stress measuring temperature, and PA1 E is Young's modulus of film.
Therefore, all thermal cycles result in thermal stress in each layer as well as in all underlying layers. The stress can be up to 5.times.10.sup.9 dynes/cm.sup.2 or even larger. The relaxation of stress results in metal failure, dielectric cracking, and defects in the silicon substrate.
The intermetal dielectric is a critical layer in the fabrication of submicron multilevel VLSI circuits. The sandwich structure of silicon oxide and spin-on-glass is widely used to form the intermetal dielectric. Referring to FIG. 1, there is shown a portion of an integrated circuit of the conventional prior art process. Field oxide region 12 has been formed in and on semiconductor substrate 10. Device structures such as gate electrodes 14 and source/drain regions 15 have been formed. Contact or via openings are formed through an insulating layer 16 to the semiconductor substrate 10 and elsewhere as shown in FIG. 1. A first metal 20 is deposited and patterned to complete the contacts. The typical sandwich structure of silicon oxide 21, spin-on-glass 23, and silicon oxide 25 is shown. Openings are made through this intermetal dielectric sandwich 21/23/25 to the first metal layer 20. A second metallization 34 is deposited and patterned. Passivation layer 35 is deposited over the patterned metal layer. Thermal stress after metallization causes stress release-induced cracks 33 shown in FIG. 2.
U.S. Pat. No. 5,119,164 to Sliwa, Jr. et al describes a method of forming voids within a spin-on-glass layer to relieve stresses leading to cracking of the spin-on-glass layer. The present invention provides a new method of forming voids within a spin-on-glass layer.